Data transfer circuit and data transfer method

专利摘要:
Provided are a data transmission circuit and a method capable of minimizing a transmission time when transmitting the same data to a plurality of data registers. Auxiliary registers 21 and write timing determination means 30 corresponding to each of the plurality of data registers are provided in the data transfer circuit for storing parallel data transferred through the data bus 14 in the plurality of data registers 20. Each auxiliary register setting means 31 stores a predetermined one bit of data 15 in the parallel data transmitted through the data bus at the first timing, and each write timing determining means is stored in each auxiliary register. According to the data of the bits, parallel data transmitted through the data bus at a second timing slower than the first timing is stored in each data register.
公开号:KR20020076118A
申请号:KR1020020015017
申请日:2002-03-20
公开日:2002-10-09
发明作者:히로후지마사유키
申请人:안도덴키 가부시키가이샤；
IPC主号:

专利说明:

Data transfer circuit and data transfer method
[31] The present invention relates to a data transfer circuit and method for minimizing a data transfer time to a data register.
[32] Fig. 5 is a block diagram showing the configuration of circuit blocks 300-x (x = 1, 2, ..., n (n is an integer of 2 or more)) included in the conventional data transmission circuit. The circuit block 300-x includes a data register 20 for storing data transmitted through the data bus 14 and a write AND gate 30 for supplying the write block 16 to the data register 20. Include.
[33] The write AND gate 30 inputs the write signal 11 and the write address signal 13 shown in FIG. 6 to take the logical product of these inputs and output the result as the write clock 16. The data register 20 receives and stores several bits of parallel data through the data bus 14 at a timing at which the write clock 16 is input. The data register 20 outputs the stored multiple bits of parallel data to the outside of the circuit block 300-x.
[34] The number of bits of data stored in the data register 20 may be equal to or less than the bus width (bit number) of the data bus 14. Here, the number of bits of data stored in the data register 20 and The bus width (number of bits) of the data bus 14 is assumed to be 32 bits.
[35] 7 is a block diagram showing the overall configuration of a conventional data transmission circuit 350. The data transmission circuit 350 has n (n is an integer of 2 or more) circuit blocks 300-1, 300-2, ..., 300-n, and each output has n (n is an integer of 2 or more). Inputs are made to the drivers 103-1, 103-2, ..., 103-n. The outputs of the drivers 103-1, 103-2, ..., 103-n are connected to test pins (not shown) of a semiconductor test apparatus (not shown), for example, for testing from these test pins to a semiconductor under test (not shown). Supply the signal.
[36] A data bus 14 is connected to the CPU 101 that controls the entire system (for example, a semiconductor test apparatus), and the CPU 101 sends 32 bits of parallel data to the data bus 14. The data bus 14 is connected to the data registers 20 in the circuit blocks 300-1, 300-2, ..., 300-n. That is, the data register 20 in each of the circuit blocks 300-1, 300-2, ..., 300-n inputs 32 bits of parallel data through the data bus 14.
[37] An address bus 19 is further connected to the CPU 101, and the CPU 101 sends an address to the address bus 19. The address sent over the address bus 19 is input to the decoder 102 and converted into a write address signal 13 at this decoder 102. The decoder 102 is in a state in which one of the plurality of write address signals 13 is output or nothing is output in accordance with the input address. The plurality of write address signals 13 are input to the write AND gates 30 in the circuit blocks 300-1, 300-2, ..., 300-n, respectively.
[38] The CPU 101 outputs the write signal 11 to the data register 20 to write (store) data. The write signal 11 is input to the write AND gate 30 in all the circuit blocks 300-1, 300-2, ..., 300-n.
[39] Next, the operation of this data transmission circuit 350 will be described. First, the CPU 101 outputs an address showing the circuit block 300-1 to the address bus 19. The sent address is input to the decoder 102, which outputs the write address signal 13 only to the circuit block 300-1.
[40] The CPU 101 sends out the address showing the circuit block 300-1 to the address bus 19 and writes the data register 20 in the circuit block 300-1 to the data bus 14 at the same time. Sends 32 bits of parallel data (to be memorized).
[41] In this state, the CPU 101 outputs a pulse of the write signal 11. The output pulse of the write signal 11 is input to the write AND gate 30 in the circuit block 300-1, and the write AND gate 30 sends the write block 16 to the data register 20. The data register 20 then stores 32 bits of parallel data sent from the CPU 101 via the data bus 14.
[42] The above operation is repeated for the circuit blocks 300-2, ..., 300-n. 32-bit data stored in the data register 20 in the circuit blocks 300-1, 300-2, ..., 300-n are stored in the data register 20 by the drivers 103-1, 103-2,... 103-n) and the drivers 103-1, 103-2, ..., 103-n supply a signal for testing the semiconductor under test, for example, to a test pin of the semiconductor test apparatus.
[43] In the prior art, n pieces of write address signals 13 are required if there are n circuit blocks, and the same number of times as the number of data registers 20 is used even when the same data is transmitted to the data registers 20 in the plurality of circuit blocks. The transmission via the data bus 14 must be made. In other words, as the system becomes larger and the number of data registers 20 increases, the transfer time becomes longer in proportion to the number of data registers 20.
[44] The present invention has been made to solve the above problems, and provides a data transmission circuit and method capable of minimizing a transmission time when the same data is transmitted to a plurality of data registers.
[1] 1 is a block diagram showing the configuration of a circuit block 100-x included in a data transmission circuit in the first embodiment of the present invention.
[2] 2 is a block diagram showing the overall configuration of the data transmission circuit 150 in the first embodiment of the present invention.
[3] 3 is a block diagram showing the configuration of a circuit block 200-m-x included in the data transmission circuit in the second embodiment of the present invention.
[4] 4 is a block diagram showing the overall configuration of the data transmission circuit 250 in the second embodiment of the present invention.
[5] 5 is a block diagram showing the configuration of a circuit block 300-x included in a conventional data transmission circuit.
[6] 6 is a timing chart showing an operation of a circuit block 300-x included in a conventional data transmission circuit.
[7] 7 is a block diagram showing the overall configuration of a conventional data transmission circuit 350.
[8] <Explanation of symbols for the main parts of the drawings>
[9] 11 light signal
[10] 12 Auxiliary Address Signal
[11] 13 write address signal
[12] 14 data bus
[13] 15 data
[14] 16 write clock
[15] 17 gate signal
[16] 18 auxiliary clock
[17] 19 address bus
[18] 20 data registers
[19] 21 auxiliary registers
[20] 30 write AND gate (write timing determining means)
[21] 31 Secondary AND Gate
[22] 100-x, 200-m-x, 300-x circuit blocks
[23] 101 CPU
[24] 102 decoder
[25] 103-1, 103-2,... , 103-n driver
[26] 103-1-1, 103-1-2,... , 103-1-n driver
[27] 103-2-1, 103-2-2,... , 103-2-n driver
[28] 150, 250, 350 data transmission circuit
[29] BS1, BS2 Block Cell
[30] 18-1, 18-2 Block Cell Signal
[45] The invention described in claim 1 for achieving the above technical problem is a data transfer circuit for storing first parallel data transmitted via a data bus in a plurality of data registers, the data bus corresponding to each of the plurality of data registers. A plurality of auxiliary registers for storing data for indicating whether or not to store the first parallel data transmitted through a data register corresponding to the first parallel data and each of the second parallel data transmitted through the data bus; Auxiliary register setting means for storing predetermined one-bit data allocated to the registers in the respective auxiliary registers at a first timing, and writing the first parallel data into the data register as the predetermined one-bit data. Phase corresponding to the auxiliary register that stores the data to indicate A data transfer circuit having a write timing decision means for storing said first parallel data to be transmitted over the data bus with a second timing later than said first timing for the data register.
[46] Further, in the invention according to claim 2, the plurality of data registers are classified into a predetermined number of block cells, and the auxiliary register setting means determines whether or not the predetermined one bit data is stored in each of the auxiliary registers. A data transmission circuit according to claim 1 for determining.
[47] In addition, the invention as set forth in claim 3 is a data transfer method for storing first parallel data transmitted through a data bus in a plurality of data registers, each of a plurality of auxiliary registers corresponding to each of the plurality of data registers. Predetermined one-bit data allocated to each of the auxiliary registers among the second parallel data for indicating whether or not the first parallel data transmitted through the data bus is to be stored in the respective data registers is designated as a first timing. A first step of storing the data register corresponding to an auxiliary register storing data instructing writing of the first parallel data into the data register by the write timing determining means as the predetermined 1-bit data; The first other data is transmitted to the first parallel data transmitted through the data bus. A method of transmitting data having a second step of storing the second timing later than humming.
[48] In the invention described in claim 4, the plurality of data registers are classified into a predetermined number of block cells. In the first step, whether or not the predetermined one bit of data is stored in each of the auxiliary registers is determined for each of the block cells. It is the data transmission method of Claim 3 to determine.
[49] [First Embodiment]
[50] 1 is a block diagram showing the configuration of a circuit block 100-x (x = 1, 2, ..., n (n is an integer of 2 or more)) included in a data transmission circuit in the first embodiment of the present invention. to be. The circuit block 100-x includes a data register 20 for storing data transmitted through the data bus 14 and a write AND gate 30 for supplying the write clock 16 to the data register 20. And an auxiliary register 21 for supplying the gate signal 17 to the write AND gate 30, and an auxiliary AND gate 31 for supplying the auxiliary clock 18 to the auxiliary register 21.
[51] The auxiliary AND gate 31 inputs the write signal 11 and the auxiliary register signal 12 to take the logical product of these inputs and output the result as the auxiliary clock 18. The auxiliary register 21 is a one-bit register that receives and stores data 15 (one bit of data) at a timing at which the auxiliary clock 18 is input. The auxiliary register 21 outputs the stored 1-bit data as the gate signal 17.
[52] The write AND gate 30 inputs the gate signal 17, the write signal 11, and the write address signal 13 to take these input logical products and output the result as the write clock 16. The data register 20 receives and stores a plurality of bits of parallel data through the data bus 14 at a timing at which the write clock 16 is input. The data register 20 outputs the stored plural-bit parallel data to the outside of the circuit block 100-x.
[53] The number of bits of data stored in the data register 20 should be less than or equal to the bus width (bit number) of the data bus 14. However, in the present embodiment, the data stored in the data register 20 is used for easy explanation. It is assumed that both the number of bits and the bus width (number of bits) of the data bus 14 are 32 bits.
[54] 2 is a block diagram showing the overall configuration of the data transmission circuit 150 in this embodiment. The data transmission circuit 150 has n (n is an integer of 2 or more) circuit blocks 100-1, 100-2, ..., 100-n, and each output has n (n is an integer of 2 or more). Inputs are made to the drivers 103-1, 103-2, ..., 103-n. The outputs of the drivers 103-1, 103-2, ..., 103-n are connected to, for example, test pins (not shown) of the semiconductor test apparatus (not shown) and from these test pins to the semiconductor under test (not shown). Supply the test signal.
[55] A data bus 14 is connected to the CPU 101 that controls the entire system (for example, a semiconductor test apparatus), and the CPU 101 sends 32 bits of parallel data to the data bus 14. The data bus 14 is connected to the data registers 20 in the circuit blocks 100-1, 100-2, ..., 100-n. That is, the data register 20 in each of the circuit blocks 100-1, 100-2, ..., 100-n inputs 32 bits of parallel data through the data bus 14.
[56] At the same time, one of the 32 (32-bit) data lines constituting the data bus 14 is connected to the auxiliary registers 21 in the circuit blocks 100-1, 100-2, ..., 100-n. . That is, in each bit in the 32-bit parallel data sent through the data bus 14, data (one bit of data) is stored in each of the circuit blocks 100-1, 100-2, ..., 100-n. It is supplied as (15) and input to the auxiliary register 21 in each of the circuit blocks 100-1, 100-2, ..., 100-n. For example, data at 'bit 1' in 32-bit parallel data sent through the data bus 14 is input to the circuit block 100-1, and data at 'bit 2' in the parallel data is inputted to the circuit block ( 100-2).
[57] An address bus 19 is also connected to the CPU 101, and the CPU 101 sends an address to the address bus 19. The address sent via the address bus 19 is input to the decoder 102 and converted into an address signal by the decoder 102. The decoder 102 is in a state in which only the auxiliary address signal 12 is output, only the write address signal 13 is output, or neither signal is output, depending on the input address. Here, the decoder 102 outputs only the auxiliary address signal 12 when the input address is the 'secondary address', and outputs only the write address signal 13 when the input address is the 'write address', except otherwise. No signal is output.
[58] The auxiliary address signal 12 output by the decoder 102 is input to the auxiliary AND gate 31 in each of the circuit blocks 100-1, 100-2, ..., 100-n, and output by the decoder 102. The write address signal 13 is input to the write AND gate 30 in each of the circuit blocks 100-1, 100-2, ..., 100-n.
[59] The CPU 101 outputs a write signal 11 which causes data writing (memory) to the data register or the like. The write signal 11 is input to the auxiliary AND gate 31 and the write AND gate 30 in all the circuit blocks 100-1, 100-2, ..., 100-n.
[60] Next, the operation of the present embodiment will be described. First, the CPU 101 sends out the 'auxiliary address' to the address bus 19. The sent 'auxiliary address' is input to the decoder 102, and the decoder 102 outputs an auxiliary address signal 12. The output auxiliary address signal 12 is input to the auxiliary AND gate 31 in each of the circuit blocks 100-1, 100-2, ..., 100-n.
[61] Next, the CPU 101 sends the data 15 to the data bus 14 to the auxiliary register 21 in each of the circuit blocks 100-1, 100-2, ..., 100-n and then writes the write signal. The pulse of (11) is output. The pulse of the output write signal 11 is input to the auxiliary AND gate 31 in each circuit block 100-1, 100-2, ..., 100-n, and the auxiliary AND gate 31 is the auxiliary clock 18 ) Is sent to the auxiliary register 21. The auxiliary register 21 then stores the data 15 sent from the CPU 101 through each bit of the data bus 14. The stored data is output as the gate signal 17 from the auxiliary register 21, and this gate signal 17 is input to the write AND gate 30.
[62] Next, the CPU 101 sends a 'write address' to the address bus 19. The sent 'write address' is input to the decoder 102, which outputs the write address signal 13. The output write address signal 13 is input to the write AND gate 30 in each of the circuit blocks 100-1, 100-2, ..., 100-n.
[63] The CPU 101 sends out a 'write address' to the address bus 19 and at the same time the data registers 20 in all the circuit blocks 100-1, 100-2, ..., 100-n on the data bus 14; Sends 32-bit parallel data to be written (remembered).
[64] In this state, the CPU 101 outputs a pulse of the write signal 11. The pulse of the output write signal 11 is input to the write AND gate 30 in each circuit block 100-1, 100-2, ..., 100-n, and the gate signal 17 is H (high level). The write AND gate 30 then sends the write clock 16 to the data register 20. The data register 20 then stores 32 bits of parallel data sent from the CPU 101 via the data bus 14. The 32-bit data stored is sent from the data register 20 to the drivers 103-1, 103-2, ..., 103-n, and the drivers 103-1, 103-2, ..., 103-n are For example, a signal for testing a semiconductor under test is supplied to a test pin of the semiconductor test apparatus.
[65] In other words, first, '1' is written only in the auxiliary register 21 in the circuit block to which the same data is written to the data register 20 among the n circuit blocks, and then, the parallel is sent through the data bus 14. Data is written to the data register 20 in the circuit block for which a plurality of writes are to be executed in one transfer. This can reduce the number of transmissions.
[66] Furthermore, when the number n of circuit blocks is larger than the number of bits (32 bits in this embodiment) of the data bus 14, the decoder 102 outputs a plurality of auxiliary address signals 12, and the auxiliary register 21 We divide in) into several times and perform. At this time, the number of auxiliary address signals 12 becomes the minimum value among integers of n / 32 or more.
[67] Second Embodiment
[68] 3 is a circuit block 200-mx (m = 1, 2, ..., X = 1, 2, ..., n (n is an integer of 2 or more) included in the data transmission circuit in the second embodiment of the present invention. Is a block diagram showing the configuration of the &quot; The circuit block 200-mx in this embodiment is different from the circuit block 100-x in the first embodiment in that the block cell signal 18-m (m = 1, 2, ...) is entered.
[69] 4 is a block diagram showing the overall configuration of the data transmission circuit 250 in this embodiment. In the present embodiment, the data transfer circuit 250 differs from the data transfer circuit 150 in the first embodiment in that a plurality of circuit blocks are divided (sorted) into a plurality of block cells. The form shows an example in which 2n circuit blocks are divided into two block cells BS1 and BS2 as an example. The block cell signals 18-1 and 18-2 for selecting the block cells BS1 and BS2 are input to the data transmission circuit 250. Moreover, these block cell signals are supplied from the CPU 101.
[70] If the block cell signals 18-1 and 18-2 are H (high level), the block cells BS1 and BS2 are selected, and 32 bits in the data register 20 in the circuit block in these block cells BS1 and BS2. Parallel data is stored.
[71] The block cell means that a pattern such as a test signal output from each block cell becomes a common pattern. In other words, it means that the data stored in the data registers 20 in the circuit blocks corresponding to each block cell are common (same). For example, the data stored in the data register 20 in the circuit block 200-1-1 in the block cell BS1 and the data register in the circuit block 200-2-1 in the block cell BS2. The data stored in 20 is common (same), and the data of the circuit block 200-1-2 of the block cell BS1 and the data of the circuit block 200-2-2 of the block cell BS2 are stored. Is common.
[72] According to the present embodiment, the common data 15 is simultaneously stored in the auxiliary register 21 in the circuit block corresponding to each block cell for storing the same data. Therefore, it is not necessary to transfer the data 15 individually for each block cell, and the data 15 can be stored simultaneously in one transfer to the auxiliary register 21 in each block cell.
[73] Further, by individually controlling the block cell signals 18-1 and 18-2, it is possible to determine whether or not to write data for each block cell.
[74] Furthermore, in each of the above embodiments, it is assumed that the data register is included in the data transfer circuit, but the data register may be provided outside the data transfer circuit.
[75] According to the present invention, in the case of transmitting the same parallel data to a plurality of data registers, one transmission is sufficient, thereby minimizing the transmission time.
[76] In addition, according to the present invention, data transmission to a plurality of block cells ends with one transmission.

权利要求:
Claims (4)
[1" claim-type="Currently amended] A data transfer circuit for storing first parallel data transferred through a data bus in a plurality of data registers,
A plurality of auxiliary registers for storing data for indicating whether or not to store the first parallel data transmitted through the data bus in a data register corresponding to the data register corresponding to each of the plurality of data registers;
Auxiliary register setting means for storing, in a first timing, predetermined one bit of data allocated to the respective auxiliary registers among the second parallel data transmitted through the data bus, in the respective auxiliary registers;
The first parallel transmitted via the data bus to the data register corresponding to the auxiliary register storing data instructing the writing of the first parallel data into the data register as the predetermined one bit of data. And a write timing determining means for storing data at a second timing slower than the first timing.
[2" claim-type="Currently amended] The method of claim 1, wherein the plurality of data registers are classified into a predetermined number of block cells,
And the auxiliary register setting means determines, for each block cell, whether or not to store the predetermined one bit of data in each of the auxiliary registers.
[3" claim-type="Currently amended] A data transfer method for storing first parallel data transmitted through a data bus in a plurality of data registers,
Among each of the plurality of auxiliary registers corresponding to each of the plurality of data registers, among the second parallel data for indicating whether or not the first parallel data transmitted via the data bus is to be stored in the respective data registers. A first step of storing, by first timing, data of a predetermined one bit allocated to each of the auxiliary registers;
The write timing determining means transfers through the data bus to the data register corresponding to the auxiliary register which stores data instructing writing of the first parallel data into the data register as the predetermined one bit of data. And a second step of storing the first parallel data in a second timing slower than the first timing.
[4" claim-type="Currently amended] The method of claim 3, wherein the plurality of data registers are classified into a predetermined number of block cells,
And determining whether or not to store the predetermined one bit of data in each of the auxiliary registers in the first step.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-03-26|Priority to JP2001088559A

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2001-03-26|Priority to JPJP-P-2001-00088559

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2002-03-20|Application filed by 안도덴키 가부시키가이샤

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2002-10-09|Publication of KR20020076118A

优先权:

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申请号 | 申请日 | 专利标题

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JP2001088559A|JP2002288121A|2001-03-26|2001-03-26|Data transfer circuit and method|

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JPJP-P-2001-00088559|2001-03-26|